Freescale Semiconductor Seminar

Spanky

Senior Member
We just returned from the Freescale Semiconductor Technology Seminar (old Motorola Semiconductor) in Orlando. We got to see first hand technology that will be used in the next level of electronic innovation.

On the cell phone front it will be TV and movies on demand in the palm of your hand. Some big dual core processors are now available to handle all the processing.

The highlight of the trip was a presentation by Neil Armstrong ( first man on the moon).

A first class experience! It would make any tecky drool! :D
 
Yes they talked about MRAM, but I did not set in on a session. Only got an introduction at the lunch presentation.

MRAM looks like the next generation of RAM if it lives up to all the hipe. Runs as fast or faster than current RAM but is non volatile when the power fails. I could imagine that if you turn off your computer and turn it back on there would be instant booting.

Based on magnetic particles holding the memory.
 
So they are giving MRAM another try, eh? I remember it from a long time ago. It was the next big thing... and never materialized.
 
TonyNo said:
So they are giving MRAM another try, eh? I remember it from a long time ago. It was the next big thing... and never materialized.
Are you sure you are not confusing it with bubble memory (also magnetic) or FRAM (Ferrous Ram)? I believe MRAM is a relatively new technology.

I got a press release about the availability of MRAM a couple of weeks ago. My impression was that it won't be able to match the low price or high density of DRAM anytime soon. But it could give SRAM and flash a run for your money.
 
Are you sure you are not confusing it with bubble memory (also magnetic) or FRAM (Ferrous Ram)?
Sort of! I saw "magnetic" and assumed "core". This looks to be very similar to core, but with some improvements, two of which are physical size and read method. Thanks for the nudge!
 
TonyNo said:
. . . This looks to be very similar to core, but with some improvements, two of which are physical size and read method.
You're right, it does! It seems to be the mechanisms of core, but implemented in silicon.
 
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