TESTEQ IP1[300] 1 OP2 explanation

Hello all,
 
could someone please help me understand this line from the examples:
TESTEQ IP1[300] 1 OP2
 
As it seems, PLC is allowing IP1 to be in its current state for 300ms, after which it changes OP2 to 1
 
Is that correct?
If yes, does it stay on the line for the 300ms or does it continue on?

Rainer

Your code will test IP1 is logic 1 longer than 300ms, if so turn on OP2, however, when IP1 having any dip, it will turn OP2 off.

TY Support,
 
You are then also saying that TESTEQ OP1[300].... does wait 300 MS until it continues to the OP2 1  portion of the command
If that is correct, two questions:
as the TESTEQ[300] waits 300ms, is it like a blocking delay (no other code continues) or does it continue with next line but returns after 300ms to turn on OP2 ?
 
Rainer

No, it's a non-blocking operation.
Internally, the PLC code says "IS OP1 1, and has it been so for 300ms??"

The answer is either yes, or no. If it's no, the result is 0, and the third operand (OP2) Is set to zero and the next instruction is skipped.
If it is yes, the result is 1, the third operand (OP2) is set to 1, and the next instruction is executed.
 
It does this every time through the code loop - which could easily be <1ms

Consider it this way, IP1[300} will be logic 1, only when input pulse longer than 300ms. Once input pulse on IP1 dips, in PLC, IP1[300] value immediately become logic 0, until next input pulse longer than 300ms.  This is to filter out shorter than 300ms 0->1 input noises.
 
Related is INVIPx, which does exactly opposite, INVIP1[300] will be logic 1, if input on IP1 pin is 0 longer than 300ms, its value in PLC is logic 1,  When input pulse stay low less than 300ms, INVIP1[300] will be logic 0.  This is to filter out shorter than 300ms 1->0 pulses.
 
If no [xyz] after IPx or INVIPx, then they function the same, immediately respond to input pin state change.

TY both!!!!
 
Rainer

it would be great if we could use that command for running averages or even quantiles, otherwise short irregularities of the signal  will ruin the logic,

Efried said:

it would be great if we could use that command for running averages or even quantiles, otherwise short irregularities of the signal  will ruin the logic,

Click to expand...

 
How do you perceive it as "ruining the logic"?
If you use the instruction as intended - eg, "has the input been stable and high for more than x milliseconds?" - I cannot see how it is possible to "ruin the logic". It is completely unambiguous. Either the input HAS been high for 300ms, or it has NOT been high for 300ms. Even a 1us low-going pulse 200ms earlier is completely unambiguously "NO, IT HAS NOT BEEN HIGH FOR 300ms or more"....
 
Perhaps I am missing your point?

Also:
is there any way to test for two logicals in one line?
 
such as: if op1 is 1 and op2 is 1 then.....
 
I see an AND operator, but it appears to be more of a ADD operator. If I am wrong, then I could use:
 
TESTEQ OP1 1 AND OP2 1
  then execute this line
 
 
Rainer

rossw said:

How do you perceive it as "ruining the logic"?
If you use the instruction as intended - eg, "has the input been stable and high for more than x milliseconds?" - I cannot see how it is possible to "ruin the logic". It is completely unambiguous. Either the input HAS been high for 300ms, or it has NOT been high for 300ms. Even a 1us low-going pulse 200ms earlier is completely unambiguously "NO, IT HAS NOT BEEN HIGH FOR 300ms or more"....
 
Perhaps I am missing your point?

Click to expand...

 
 
No you are right. I was targeting instable signals. With quantiles I could implement fuzzy rules,

rfeyer said:

Also:
is there any way to test for two logicals in one line?
 
such as: if op1 is 1 and op2 is 1 then.....
 
I see an AND operator, but it appears to be more of a ADD operator. If I am wrong, then I could use:
 
TESTEQ OP1 1 AND OP2 1
  then execute this line
 
 
Rainer

Click to expand...

 
 
I subscribe to that and would like have an ELSE too...
I think a graphical programming interface would be more appropriate, because coders will head to other solutions soon..

TSTxy command continue next line if result is TRUE, otherwise skip next line, that is effective ELSE
PLC logic do one testing per line, does not do two, not allow AND on the same line, simply because that could be confusing for others.
Because with more logic on one line, then question will be which part of the TSTxy do first, AND would still execute if one TST failed, ....etc.
 
Since CPU does one thing at a time, simple logic will lead to more reliable result.

TY for explanation - that works for me
The language is simple and usable, I am starting to get the hang of it.
 
Rainer

rfeyer said:

Also:
is there any way to test for two logicals in one line?
 
such as: if op1 is 1 and op2 is 1 then.....
 
I see an AND operator, but it appears to be more of a ADD operator. If I am wrong, then I could use:
 
TESTEQ OP1 1 AND OP2 1
  then execute this line

Click to expand...

 
I haven't tried this, but it should work...
 
  AND op1 op2         # logical AND of the two outputs
  BZ xxx                   # at least one output is not on
  (do stuff)                # both outputs are high, do required stuff
xxx:
  (rest of code)

TY RossW!!
 
I'd like to show you the code I have so far - could you all tell me if it makes any sence before I try it out?
I konw it is not possible to have comments in PLC, these will be removed
TY   Rainer
 
START
     TSTEQ URAM1 1
          CALLSUB     raise
     TSTEQ URAM1 2
          CALLSUB     lower
     TSTEQ URAM1 3
          CALLSUB     endall
 
END
 
lower:
     TSTEQ ram1 0
          CALLSUB     lowshort                 ; this will cause short bursts of buzzer and door lowering as a warning
     TSTEQ ram1 5
          CALLSUB    lowlong                    ; this will lower the rest of door - if there should be a switch fail, stops after 15 secs or so
     TSTEQ ram1 15
          CALLSUB endall
END
 
lowshort:
     INC ram1
     TSTEQ ram1 5
          RET                                                  ;? embedded END allowed?
     TSTEQ      OP1[100] 0
          SET OP1 1
     TSTEQ     OP1[100] 1
          SET OP1 0
RET
 
lowlong:
     INC ram2
     TSTEQ ram1 15
           CALLSUB endall                                                  ;? embedded END allowed?
     TSTEQ OP1[100] 0
          SET OP1 1
     TSTEQ OP1[1000] 1
          SET OP1 0
RET
 
raise:
     OP2 1
     TSTEQ OP2[15000]
          CALLSUB endall
RET
 
endall:
     ram1 0
     OP1 0
     OP2 0
     URAM1 0
RET